The present invention generally relates to a PLL synthesizer, and more particularly to a PLL synthesizer which controls the frequency of an output signal so as to be always equal to a desired frequency. The present invention is suitable for a digital tuner, for example.
A PLL (phase-locked loop) synthesizer is a feedback circuit which functions to make the frequency of an output signal equal to a desired frequency. In general, a lowpass filter is provided in the PLL loop to improve the purity of the output signal derived from the PLL synthesizer. When the desired frequency is changed to a different frequency, it takes a lock-up time for the frequency of the PLL synthesizer to be settled at the different frequency.
FIG. 1 is a block diagram of a conventional PLL synthesizer. The PLL synthesizer is supplied with a clock signal CK, set frequency data DA, and a strobe signal STB, all of which are derived from an external circuit (not shown). When the strobe signal STB is supplied to the PLL synthesizer while the set frequency data DA is being input thereto, the set frequency data DA is written into a PLL operation circuit 1 in synchronism with the clock signal CK. The PLL operation circuit 1 divides the set frequency data DA on the basis of a reference frequency generated by a crystal oscillator 2 and thereby generates a set signal fr, which is supplied to a phase comparator 3. The PLL operation circuit 1 is supplied with a signal supplied from a prescaler circuit (frequency divider) 7. The signal from the prescaler circuit 7 is frequency-divided by the PLL operation circuit 1 so that a feedback signal fp to be supplied to the phase comparator 3 is generated.
The phase comparator 3 generates pulse signals .phi.r and .phi.p which are based on the frequencies of the set signal fr and the feedback signal fp as well as the phase difference therebetween as shown in (A) and (B) of FIG. 2. The charge pump circuit 4 derives a signal SG1 as shown in (C) of FIG. 2 from the pulse signals .phi.r and .phi.p. The signal SG1 contains pulse components on a DC component thereof. This DC component of the signal SG1 is increased or decreased in response to fluctuations of the frequencies of the pulse signals .phi.r and .phi.p. The pulse components contained in the signal SG1 are varied on the basis of the phase difference between the pulse signals .phi.r and .phi.p. When the phase of the pulse signal .phi.p lags behind the phase of the pulse signal .phi.r, a high component PH out of the pulse components contained in the signal SG1 is large. On the other hand, when the phase of the pulse signal .phi.p leads the phase of the pulse signal .phi.r, a low component PL out of the pulse components contained in the signal SG1 is large.
The lowpass filter 5 smooths the signal SG1 derived from the charge pump circuit 4 and eliminates the pulse components from the signal SG1. Thereby, a signal SG2 having no pulse components is generated by the lowpass filter 5. The signal thus formed is supplied to a voltage-controlled oscillator (hereinafter simply referred to as a VCO) 6, which generates an output signal SG3 having a frequency based on the voltage of the signal SG2 supplied from the lowpass filter 5. The output signal SG3 is supplied to the prescaler circuit 7, which divides the frequency of the output signal SG3. The signal derived from the prescaler circuit 7 is further frequency-divided by the PLL operation circuit 1 so that the aforementioned feedback signal fp is generated.
When the set frequency data DA indicating a frequency F1 at present is changed so as to indicate a frequency F2 higher than the frequency F1, the PLL synthesizer shown in FIG. 1 operates as shown in FIG. 3. In response to the strobe signal STB shown in (A) of FIG. 3, the frequency fr1 of the set signal fr output from the PLL operation circuit 1 is increased to a frequency fr2 as shown in (B) of FIG. 3. In response to this change of the frequency, as shown in (C) of FIG. 3, the DC component of the signal SG1 output from the charge pump circuit 4 is increased, and the voltage of the signal SG2 is also increased as shown in (D) of FIG. 3. In response to this change of the signal SG2, the frequency of the output signal SG3 derived from the VCO 6 is changed from the frequency F1 to the frequency F2 as shown in (E) of FIG. 3. The output signal SG3 is always fed back to the PLL operation circuit 1 through the prescaler circuit 7. Thus, the frequency of the feedback signal fp is adjusted so as to become equal to the frequency fr2. Adversely, when the frequency of the set signal fr is decreased, the DC component of the signal SG1 is decreased, and the feedback signal fp is adjusted that the frequency thereof becomes equal to the decreased frequency of the set signal fr. Thus, the PLL synthesizer can generate different frequencies by the use of a single crystal oscillator 2 with a stability approximately equal to that for the crystal oscillator 2. It is noted that the pulse components contained in the signal SG1 shown in (C) of FIG. 3 are omitted for the convenience' sake.
However, the aforementioned PLL synthesizer has disadvantages as described below. The signal output from the charge pump circuit 4 is supplied to the VCO 6 through the lowpass filter 5. Thus, the PLL synthesizer needs a lock-up time t.sub.1 (FIG. 3-(E)) based on a time constant of the lowpass filter 5 until the frequency of the output signal SG3 is settled at the revised frequency F2 after the DC level of the output signal SG1 starts changing. In case where the PLL synthesizer shown in FIG. 1 is applied to a digital tuner, tuning is not available during the lock-up time t.sub.1 and a noise is introduced in the output signal SG3.
When the PLL synthesizer is designed to decrease the time constant of the lowpass filter 5 to thereby reduce the lock-up time t.sub.1, the pulse component contained in the signal SG1 derived from the charge pump circuit 4 is applied to the VCO 6 without being eliminated. This causes a deterioration of the output signal SG3 and degrades the purity of the output signal SG3.